The present invention relates to a delay locked loop (DLL) of a semiconductor device including a circuit for correcting a duty ratio of an output signal, and more particularly, to a DLL of a semiconductor device with a relatively small occupation area and relatively low current consumption even while having a function of correcting a duty ratio.
Generally, in a synchronous semiconductor memory device such as a double data rate (DDR) synchronous DRAM (SDRAM), input/output data must be always synchronized with a reference clock.
The reference clock means an external clock (CLK and CLKB) inputted from an external device, for example, a memory controller. Therefore, the meaning the synchronous semiconductor memory device must transmit data in synchronization with the reference clock is that an output point of time of the data transmitted from the synchronous semiconductor memory device must be exactly equal to an edge or center of the external clock (CLK and CLKB).
As known from asynchronous semiconductor memory devices, however, data are not always outputted in synchronization with the external clock (CLK and CLKB) even though an output command and the external clock (CLK and CLKB) are applied to general semiconductor memory devices.
The reasons that the data are not synchronized with the external clock (CLK and CLKB) in such a semiconductor memory device are as followings.
First, it is assumed that the external clock (CLK and CLKB) buffered through an input buffering circuit in the semiconductor memory device is referred to as an internal clock. The internal clock may change its phase while passing through various internal elements, e.g., a control circuit, a peripheral circuit and a cell array, of the semiconductor memory device. Accordingly, the internal clock is not synchronized with the external clock (CLK and CLKB) when the internal clock is outputted to the outside through an output buffering circuit.
Since the output data of the semiconductor memory device are outputted in synchronization with the internal clock, there is also a phase difference between the data and the external clock (CLK and CLKB), which corresponds to a phase difference between the internal clock and the external clock (CLK and CLKB). That is, the data outputted from the semiconductor memory device are asynchronous with the external clock (CLK and CLKB).
Therefore, in order to output the input/output data in synchronization with the external clock (CLK and CLKB) which is used as a reference clock in the semiconductor memory device, the internal clock must be inversely compensated for a delay time that the internal clock applied to an output pad is delayed with respect to the inputted external clock (CLK and CLKB) due to operation of the semiconductor memory device. Through such inverse compensation, the phase of the internal clock can be synchronized with the phase of the external clock (CLK and CLKB).
A phase locked loop (PLL) and a delay locked loop (DLL) are representatively used as a circuit for synchronizing the internal clock with the external clock (CLK and CLKB) by inversely compensating for the delay time that the phase of the internal clock is delayed.
The PLL is used for synchronizing a frequency and a phase at the same time using a frequency multiplication function when there is a frequency difference between the external clock, which is a reference clock mainly inputted from the outside, and the internal clock, which is used in the semiconductor memory device.
The DLL is used for synchronizing only a phase when the external clock is equal in frequency to the internal clock.
Comparing only characteristics of the PLL and the DLL themselves with each other, the PLL seems to be more popularly used than the DLL because the PLL has a supplementary function, i.e., frequency multiplication function. Actually, however, the DLL is more popularly used than the PLL in the semiconductor memory device.
There may be several reasons for this, a representative one of which is that the DLL has such advantageous merits that the DLL is less affected by noise and can be formed in a smaller area than the PLL.
FIG. 1 is a block diagram illustrating a conventional DLL of a semiconductor device.
Referring to FIG. 1, the conventional DLL of the semiconductor device includes a delay locking unit 100, a phase detection unit 120, and a phase mixing unit 140. The delay locking unit 100 generates a first delay clock RISING_CLK corresponding to a first clock edge, e.g., rising edge of a reference clock REF_CLK, and a second delay clock FALLING_CLK corresponding to a second clock edge, e.g., falling edge of the reference clock REF_CLK so as to achieve a delay-locking. The phase detection unit 120 detects a phase difference between the first delay clock RISING_CLK and the second delay clock FALLING_CLK to output a weight select signal WR_SEL. The phase mixing unit 140 mixes phases of the first and second delay clocks RISING_CLK and FALLING_CLK by applying a weight corresponding to the weight select signal WR_SEL at points of time when the first and second delay clocks RISING_CLK and FALLING_CLK are delay locked, thereby outputting DLL clocks DLL_CLK_USE and DLL_CLK_DUMMY. The conventional DLL further includes a split unit 110A and a dummy split unit 110B, which split phases of the DLL clock DLL_CLK_USE and DLL_CLK_DUMMY to generate first and second split clocks RCLKDLL and FCLKDLL. The dummy split unit 110B has the same configuration as the split unit 110A but does not operate actually.
The phase mixing unit 140 includes a delay lock enable signal generator 146, a mixing controller 142, a DCC phase mixer 144 and a dummy DCC phase mixer 145. The delay lock enable signal generator 146 generates a delay lock enable signal DCC_EN of which a logic level is determined in response to a first delay lock signal LOCK_STATE_R and a second delay lock signal LOCK_STATE_F. The first delay lock signal LOCK_STATE_R corresponds to whether the first delay clock RISING_CLK is delay locked or not, and the second delay lock signal LOCK_STATE_F corresponds to whether the second delay clock FALLING_CLK is delay locked or not. The mixing controller 142 generates a mixing control signal CTRL for controlling a mixing ratio of the first and second delay clocks RISING_CLK and FALLING_CLK in response to the weight select signal WR_SEL when the delay lock enable signal DCC_EN is activated. The DCC phase mixer 144 mixes phases of the first and second delay clocks RISING_CLK and FALLING_CLK at the mixing ratio corresponding to the mixing control signal CTRL to thereby output the DLL clock DLL_CLK_USE. The dummy DCC phase mixer 145 has the same configuration as the DCC phase mixer 144 but does not operate actually.
The delay locking unit 100 includes a first phase delay 102, a second phase delay 104, a first delay replica model 103 and a second delay replica model 105 for achieving a delay-locking. The first phase delay 102 delays a first clock CLK_IN_R corresponding to a first clock edge, e.g., rising edge, of the reference clock REF_CLK by a delay time determined through comparing phases of the reference clock REF_CLK and a first feedback clock FEB_CLK1 with each other, thereby outputting the first delay clock RISING_CLK. The second phase delay 104 delays a second clock CLK_IN_F corresponding to a second clock edge, e.g., falling edge, of the reference clock REF_CLK by a delay time determined through comparing phases of the reference clock REF_CLK and a second feedback clock FEB_CLK2 with each other, thereby outputting the second delay clock FALLING_CLK. The first delay replica model 103 outputs the first feedback signal FEB_CLK1 by applying an actual delay condition of the first clock CLK_IN_R to the first delay clock RISING_CLK. The second delay replica model 105 outputs the second feedback signal FEB_CLK2 by applying an actual delay condition of the second clock CLK_IN_F to the second delay clock FALLING_CLK. The delay locking unit 100 further includes a clock buffer 106 configured to buffer the external clocks CLK and CLKB inputted from the outside to output the reference clock REF_CLK and the first and second clocks CLK_IN_R and CLK_IN_F.
The first phase delay 102 includes a first phase comparator 1022 and a first delay line 1024. The first phase comparator 1022 compares the phase of the first feedback clock FEB_CLK1 with that of the reference clock REF_CLK to generate a first delay control signal DELAY_CON1. The first delay line 1024 delays the first clock CLK_IN_R by a delay time determined corresponding to the first delay control signal DELAY_CON1 to output the first delay clock RISING_CLK.
The second phase delay 104 includes a second phase comparator 1042 and a second delay line 1044. The second phase comparator 1042 compares the phase of the second feedback clock FEB_CLK2 with that of the reference clock REF_CLK to generate a second delay control signal DELAY_CON2. The second delay line 1044 delays the second clock CLK_IN_F by a delay time determined corresponding to the second delay control signal DELAY_CON2 to output the second delay clock FALLING_CLK.
Operation of the conventional DLL having the above configuration will be described below.
The operation of the delay locking unit 100 of the conventional DLL is mainly divided into two operation modes, of which one is an operation in a state before a delay is locked and the other is an operation in a state after a delay is locked. For convenience in description, the state before the delay is locked will be referred to as a before-delay-locked state, and the state after the delay is locked will be referred to as an after-delay-locked state, hereinafter. As described above, the operations in the before-delay-locked state and the after-delay-locked state are determined according to whether the phases of the first and second delay clocks RISING_CLK and FALLING_CLK outputted from the delay locking unit 100 fall within a predetermined range. That is, when the phases of the first and second delay clocks RISING_CLK and FALLING_CLK fall out of the predetermined range, this state may be referred to as the before-delay-locked state. On the contrary, when the phases of the first and second delay clocks RISING_CLK and FALLING_CLK fall within the predetermined range, this state may be referred to as the after-delay-locked state.
Specifically, at a point of time when the DLL of the semiconductor device starts operating in the before-delay-locked state, the first and second clocks CLK_IN_R and CLK_IN_F are the same as the reference clock REF_CLK because the reference clock REF_CLK and the first and second clock CLK_IN_R and CLK_IN_F are all generated by buffering the external clocks CLK and CLKB.
However, the first and second clocks CLK_IN_R and CLK_IN_F are delayed by predetermined initial delay times and have opposite phases to each other, respectively, while passing through each of the first and second delay lines 1024 and 1044. Therefore, there are phase differences between the reference clock REF_CLK, and the first and second delay clocks RISING_CLK and FALLING_CLK.
That is, the first delay clock RISING_CLK has a rising edge at a point of time after a lapse of the initial delay time from a point of time corresponding to a first edge of the reference clock REF_CLK. Herein, the first edge of the reference clock REF_CLK is assumed to be a rising edge. The second delay clock FALLING_CLK has a falling edge at a point of time after a lapse of the initial delay time from a point of time corresponding to a second edge of the reference clock REF_CLK. Herein, the second edge of the reference clock REF_CLK is assumed to be a falling edge.
Thereafter, the first delay clock RISING_CLK is delayed by a delay time set in the first delay replica model 103 and then outputted while the DLL of the semiconductor device starts operating. The delay time, i.e., delay amount, set in the first replica model 103 is equal to the delay time of the first clock CLK_IN_R that is delayed while passing through various internal elements, e.g., a control circuit, a peripheral circuit and a cell array, of the semiconductor memory device.
Likewise, the second delay cock FALLING_CLK is delayed by a delay time set in the second delay replica model 105 and then outputted. The delay time of the second delay clock FALLING_CLK by the second delay replica model 105 is equal to the delay time of the first delay clock RISING_CLK by the first delay replica model 103. In other words, the delay time of the first clock CLK_IN_R delayed while passing through the internal elements of the semiconductor memory device is equal to the delay time of the second clock CLK_IN_F delayed while passing through the internal elements of the semiconductor memory device.
In FIG. 1, however, it can be appreciated that the first and second delay clocks RISING_CLK and FALLING_CLK are not inputted to the first and second delay replica models 103 and 105 but the DLL clock DLL_CLK_USE and the dummy DLL clock DLL_CLK_DUMMY are inputted to the first and second delay replica models 103 and 105, respectively. This is because the phase mixing unit 140 does not operate in the before-delay-locked state but operates in only the after-delay-locked state.
That is, the phase mixing unit 140 serves as a bypass in the before-delay-locked state to thereby output an input signal as its entirety. However, the phase mixing unit 140 mixes phases of input signals in the after-delay-locked state.
Therefore, in the before-delay-locked state, it can be appreciated that the first and second delay clocks RISING_CLK and FALLING_CLK inputted to the phase mixing unit 140 are the same as the DLL clock DLL_CLK_USE and the dummy DLL clock DLL_CLK_DUMMY outputted from the phase mixing unit 140, respectively.
The conventional DLL of the semiconductor device performs an operation for changing clocks in the before-delay-locked state until existing the before-delay-locked state.
First, a rising edge of the first delay clock RISING_CLK outputted from the first delay line 1024 is delay locked, i.e., synchronized, with a rising edge of the reference clock REF_CLK by appropriately controlling the first delay line 1024 such that the first clock CLK_IN_R having the initial delay time is further delayed by a first predetermined time.
At the same time, a rising edge of the second delay clock FALLING_CLK outputted from the second delay line 1044 is delay locked, i.e., synchronized, with the rising edge of the reference clock REF_CLK by appropriately controlling the second delay line 1044 such that the second clock CLK_IN_F having the initial delay time is further delayed by a second predetermined time.
The first delay line 1024 delaying the first clock CLK_IN_R differs in delay amount from the second delay line 1044 delaying the second clock CLK_IN_F. That is, the first predetermined time and the second predetermined time are different from each other.
As described above, the rising edge of the first delay clock RISING_CLK is synchronized with the rising edge of the reference clock REF_CLK so that the first delay lock signal LOCK_STATE_R is activated, and the rising edge of the second delay clock FALLING_CLK is synchronized with the rising edge of the reference clock REF_CLK so that the second delay lock signal LOCK_STATE_F is activated. Consequently, the delay lock enable signal DCC_EN is activated so that the before-delay-locked state is terminated.
Afterwards, the DLL of the semiconductor device enters an operation mode in the after-delay-locked state. In the after-delay-locked state, the phase mixing unit 140 does not serve as a bypass but mixes phases of the inputted first and second delay clocks RISING_CLK and FALLING_CLK, thus correcting a duty ratio of the DLL clock DLL_CLK_USE outputted from the phase mixing unit 140 at 50 to 50.
In consideration of the reason that the DLL exists in the semiconductor device as aforementioned, the DLL is required for synchronizing the internal clock with the external clock by inversely compensating for a delay time that the phase of the internal clock is delayed due to the operation of the semiconductor device.
That is, when exiting the before-delay-locked state, the rising edges of the DLL clocks DLL_CLK_USE and DLL_CLK_DUMMY, i.e., the internal clock, are in synchronization with the rising edge of the reference clock REF_CLK, i.e., the external clock. Herein, the DLL clocks DLL_CLK_USE and DLL_CLK_DUMMY may be equal to the first and second delay clocks RISING_CLK and FALLING_CLK at a point of time when the before-delay-locked state is terminated. Therefore, operation of the DLL must be stopped at the same time when the before-delay-locked state is terminated.
However, while an early semiconductor device outputs one data within one period of the internal clock, a state-of-the art semiconductor device outputs two or more data within one period of the internal clock.
For example, there have been developed several semiconductor memory devices including synchronous semiconductor memory devices such as DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM, in which one data is outputted at a rising edge of the DLL clock DLL_CLK_USE and another data is also outputted at a falling edge of the DLL clock DLL_CLK_USE.
If a logic high level section of the internal clock from the rising edge to the falling edge is relatively long but a logic low level section from falling edge to the rising edge is relatively short, a time is enough to input/output data during the logic high level section but a time is not enough to input/output data during the logic low level section. This may lead to an error in inputting/outputting data.
Therefore, operation of correcting the duty ratio of the DLL clock DLL_CLK_USE, internal clock, must be performed at the end of the DLL.
Specific operation of the mixing controller 142 in the after-delay-locked state will be described below. A logic high level section of the first delay clock RISING_CLK is equal to a logic high level section of the reference clock REF_CLK, and a logic high level section of the second delay clock FALLING_CLK is equal to a logic high level section of the reference clock REF_CLK. Since the rising edges of the first and second delay clocks RISING_CLK and FALLING_CLK are synchronized in the before-delay-locked state, the phase detection unit 120 compares the falling edge of the first delay clock RISING_CLK with the falling edge of the second delay clock FALLING_CLK to thereby output the weight select signal WR_SEL.
Thereafter, the mixing controller 142 appropriately controls the mixing control signal CTRL such that the DCC phase mixer 144 mixes the phases of the first and second delay clocks RISING_CLK and FALLING_CLK with a weight corresponding to the weight select signal WR_SEL.
Through the above-described procedure, the DCC phase mixer 144 generates the DLL clock DLL_CLK_USE having a duty ratio of 50 to 50.
Afterwards, the split unit 110A splits the DLL clock DLL_CLK_USE with a corrected duty ratio of 50 to 50, thus generating a first split clock RCLKDLL corresponding to the first edge, e.g., rising edge, of the DLL clock DLL_CLK_USE and a second split clock FCLKDLL corresponding to the second edge, e.g., falling edge, of the DLL clock DLL_CLK_USE.
At this time, it is unnecessary for the dummy DCC phase mixer 145 and the dummy phase split unit 110B to be operated. This is because the dummy DCC phase mixer 145 and the dummy phase split unit 110B serve as a load having resistance corresponding to resistance of elements, e.g., inverts and transistors, in the dummy DCC phase mixer 145 and the dummy phase split unit 110B, so that they are used for bypassing the first and second delay clocks RISING_CLK and FALLING_CLK inputted to the phase mixing unit 140 under the same transmission condition in the before-delay-locked state. Accordingly, the dummy DCC phase mixer 145 and the dummy phase split unit 110B may not operate in the after-delay-locked loop except that it performs only a bypass operation in the before-delay-locked state.
Through the operations in the before-delay-locked state and the after-delay-locked state of the conventional DLL, the DLL clock DLL_CLK USE accomplishing two objects below is generated.
A first object to inversely compensate for the time delay of the internal clock for synchronizing output data with the external clock has been accomplished in the before-delay-locked state of the DLL.
A second object is not to output data at only the first edge, e.g., rising edge, of the internal clock but to output data both the first edge and the second edge, e.g., falling edge, by accurately correcting the duty ratio of the internal clock at 50 to 50. Therefore, the second object has been accomplished in the after-delay-locked state.
To accomplish the two objects as above, the conventional DLL of the semiconductor device in FIG. 1 operates in dual loop manner so that some elements of the DLL are not operated substantially but left untended according to whether the operation mode is in the before-delay-locked state or the after-delay-locked state.
For reference, a great difference between the DLL using a dual loop and the DLL using a single loop is number of the internal clocks. That is, the DLL using the single loop uses one internal clock when synchronizing the internal clock with the external clock, whereas the DLL using the double loop uses two internal clocks. This has been publicly well known, and thus further description for it will be omitted herein.
For example, the mixing controller 140 cannot perform the correction operation of the duty ratio in the before-delay-locked state but bypasses the input signal as its entirety. Because the bypassing means just connecting a line, it can be understood that the mixing controller 140 does not operate substantially in the before-delay-locked state.
Further, even during the intrinsic duty correction in the after-delay-locked state, the mixing controller 140 does not use the dummy DCC phase mixer 145 which has been used as a load having predetermined resistance during the bypass operation in the before-delay-locked state.
In the delay locking unit 100, the elements related to the first delay clock RISING_CLK, e.g., first phase delay 102 and the first delay replica model 103, are still used in both the before-delay-locked state and the after-delay-locked state, whereas operations of the elements related to the second delay clock FALLING_CLK, e.g., second phase delay 104 and the second delay replica model 105, are not meaningful in the after-delay-locked state.
This is because the DLL clock DLL_CLK_USE is a clock corresponding to the first delay clock RISING_CLK. In the case where the DLL clock DLL_CLK_USE is a clock corresponding to the second delay clock FALLING_CLK, the operations of the elements related to the first delay clock RISING_CLK, e.g., first phase delay 102 and the first delay replica model 103, may not be meaningful in the after-delay-locked state.
Also, because the dummy phase split unit 110B, which is connected to an output terminal of the phase mixing unit 140 and compared to the split unit 110A for splitting the DLL clock DLL_CLK_USE, is used as a load having predetermined resistance during a bypass operation in the before-delay-locked state, the dummy phase split unit 1108 is not used in the after-delay-locked state.
In this way, even though some elements of the DLL are not operated substantially but left untended, the conventional DLL employing the dual loop in FIG. 1 can be normally operated only if all the elements are included.
If, however, the DLL employs the single loop in order to overcome a problem of the conventional DLL employing the dual loop, it is easy to accomplish the first object to inversely compensate for the time delay of the internal clock for synchronizing output data with the external clock but there is no way to accomplish the second object to accurately maintain the duty ratio of the internal clock at 50 to 50.
Accordingly, in the conventional art, the DLL employing the dual loop has been used in the semiconductor device inevitably, leading to a problem of large occupation area of the DLL.
Therefore, as the semiconductor device is shrinking in size, the application of the DLL employing the dual loop makes it difficult to miniaturize the semiconductor device.
In addition, even in a state that some elements of the DLL employing the dual loop are not operated substantially but left untended, current still flows into those elements, thus giving rise to unnecessary current consumption.
Consequently, as the semiconductor device with lower power consumption is being developed, the application of the DLL with the dual loop makes it difficult to achieve the semiconductor device with low power performance.